20180106

Vulnerability of Speculative Processors to Cache Timing Side-Channel Mechanism

【外部リンク】
Vulnerability of Speculative Processors to Cache Timing Side-Channel Mechanism
Updated on 03/Jan/2018

https://developer.arm.com/support/security-update
Variant 1: bounds check bypass (CVE-2017-5753)
Variant 2: branch target injection (CVE-2017-5715)
Variant 3: rogue data cache load (CVE-2017-5754)
In addition, Arm has included information on a related variant to 3, noted as 3a, in the table below.

Follow the steps below to determine if there is any vulnerability for your devices and, if vulnerable, then the mitigation mechanisms.

Step 1
Check the table below to determine if you have an affected processor.
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注目の投稿

Shadowserver Foundation http://65.49.1.117/

Shadowserver Foundation port 14491 discarded for LINK-FRMWRK: NO ENTRY IN LOOKUP TABLE TO COMPLETE OPERATION, GigaEthernet2.0 Wistron Neweb ...

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